I. Field
The present disclosure generally relates to systems and methods of power distribution in a circuit, and more particularly to systems and methods using low-resistance package metals to distribute switched power or signals to designated areas of a silicon substrate.
II. Description of Related Art
Advances in technology have resulted in smaller and more powerful personal computing devices. For example, a variety of portable personal computing devices, including wireless computing devices, such as portable wireless telephones, personal digital assistants (PDAs), and paging devices are small, lightweight, and easily carried by users. More specifically, portable wireless telephones, such as cellular (analog and digital) telephones and IP telephones, can communicate voice and data packets over wireless networks. Further, many such wireless telephones include other types of devices that are incorporated therein. For example, a wireless telephone can also include a digital still camera, a digital video camera, a digital recorder, and an audio file player. Also, such wireless telephones can include a web interface that can be used to access the Internet. As such, these wireless telephones include significant computing capabilities.
Within such devices, the circuitry is becoming smaller, and power consumption by the circuitry is becoming increasingly significant to performance. A typical integrated circuit includes a substrate, which may include a plurality of embedded circuit structures, as well as one or more integrated circuit devices that are electrically coupled to the substrate. A large number of such circuit devices are made using designs in which the input/output (I/O) circuits can be placed in different locations and are not limited to the periphery of the chip. This type of device can be referred to as a flip chip. The flip chip technology allows an integrated circuit device or package to be physically and electrically coupled to a substrate by inverting and bonding the package face down to the substrate interconnection pattern, using raised metallic bonding bumps on each of the package mounting pads corresponding to the conductive pads or areas on the substrate. The bonding bumps or balls join the conductive pads of the package to the conductive areas on the substrate by using controlled reflow solder techniques or conductive epoxy techniques.
One aspect of the physical design of flip chips relative to input/output (I/O) circuits is the sizing and routing of the wiring that connects the I/O circuits to the appropriate on-chip power distribution networks. Power routing of flip chip circuits is the process of connecting the power service terminals of each I/O pin of the flip chip circuit to the power distribution network of the substrate to supply power to circuitry of the flip chip. In general, the power service terminals are coupled to the power distribution network by metal wires or traces, which may be referred to as power routes. By controlling the widths of the power routes, the effective resistance and the current densities of the power routes can be controlled to satisfy the electrical requirements of a design.
As chips have become smaller, the resistance of metal layers within a silicon substrate has increased while the power densities have also increased. To address the increased power densities, additional thick metal layers may be added for power redistribution to lower the resistive losses in the distribution network. However, such designs increase routing complexity and decrease available area for component layout on the substrate.
Accordingly, it would be advantageous to provide an improved power distribution system and method that reduces power loss and thermal loads and that allows for continued process scaling.